In recent years, with a reduction in the size of electronic components and an increase in mounting density, high positional accuracy has been demanded when electronic components are mounted on a substrate. When the electronic components are mounted by a method of mounting electronic components on cream solder printed on electrodes of a substrate and of soldering the electronic components by reflow, it is desirable to mount the electronic components in consideration of the operation thereof in the reflow process and to manage the positional accuracy.
Therefore, the following method has been proposed: the positions of solder printed on a substrate are measured prior to a component mounting operation, and electronic components are mounted on the positions of solder when the electronic components are mounted (for example, see Japanese Unexamined Patent Application Publication No. 2002-84097). According to this method, in the reflow process in which electronic components are connected to electrodes by melt solder, it is possible to mount the electronic components on the electrodes of the substrate, without damaging the self-alignment effect of the melt solder, and thus to prevent defects in mounting due to the positional deviation of solder.
However, in the technique disclosed in JP-A-2002-84097, since a design is performed for solder printing positions with respect to a number of electrodes formed on a substrate, it takes much time to measure the solder printing positions before a component mounting operation. As a result, tact-time required for the mounting operation is delayed, which makes it difficult to prevent defects in mounting due to the positional deviation of the printed solder and to achieve high productivity.